Non-volatile memory (“NVM”) cells are fabricated in a large variety of structures, including but not limited to: (1) poly-silicon floating gate, (2) Non volatile MIRRORBIT, (3) Silicon-Oxide-Nitride-Oxide-Silicon (“SONOS”), and others. FIGS. 1A through 1C show cross-sectional views of several different NVM cell structures. Although each NVM cell structure has unique properties and operating characteristics, basic operation of NMV cells, sets or arrays of NVM cells, and devices based on these NVM cells is fundamentally similar. NVM cells are programmed (i.e. charged or discharged) to a logical state correlated with information (e.g. bits) they are to store and read by detecting their threshold voltages (Vt).
Information is stored on NVM cells by regulating and altering the NVM cell's logical state, which logical state may be defined and determined by adjusting and later reading its Vt—the gate to source voltage at which the NVM cell begins to conduct non-negligible current. Different threshold voltage ranges are associated with different logical states, and a NVM cell's threshold voltage level may be correlated to the amount of charge (e.g. electrons) stored in a charge storage region of the cell. FIG. 2A shows a voltage distribution graph depicting possible threshold voltage distributions of a binary non-volatile memory cell, wherein vertical lines depict boundary voltage values correlated with each of the cell's possible states. Cells having Vt lower than EV level are said to be erased verified. Cells having Vt higher than PV are said to be program verified. Since NVM cells may lose some amounts of stored charge, a read verify level above which the cell is also considered programmed, may be set below a program verify level. A Program sequence of programming pulses may be used to drive the Vt of a cell higher than PV, while an erase sequence may drive the cell's Vt lower than EV.
FIG. 2B shows a voltage distribution graph depicting possible threshold voltage distributions in the charge storage region of a multi-level non-volatile memory cell (“MLC”), wherein one set of vertical lines depict boundary values correlated with each of the cell's possible Program Verify Threshold Voltages (PV00, PV01, etc.), another set of vertical lines depict boundary values correlated with the Read Verify level of each of the cell's possible Program states (RV00, RV01, etc.), and yet another set depict boundary lines for Intermediate Program Verify voltages (PVI 00, PVI 01, etc.) associated with each of the states.
The amount of charge stored in a charge storage region of an NVM cell, may be increased by applying one or more programming pulses to the cell. While the amount of charge in the cell may decrease by applying an erase pulse to the NVM cell which may force the charge reduction in the cell's charge storage region, and consequently may decrease the NVM's Vt.
Most methods of operating NVM cells (e.g. programming, reading, and erasing) require one or more reference structures, such as reference cells, to generate the reference levels against which the Vt of a cell is compared. Each of the one or more reference structures may be compared against a memory cell being operated in order to determine a Vt, condition or state of the memory cell being operated. Generally, in order to determine whether an NVM cell is at a specific state, for example erased, programmed, or programmed at one of multiple possible program states within a multi-level cell (“MLC”), the cell's threshold level is compared to that of a reference structure whose threshold level is preset and known to be at a voltage level associated with the specific state being tested for.
Comparing the threshold voltage of an NVM cell to that of a reference cell is often accomplished using a sense amplifier. Various techniques for comparing an NVM threshold voltage against those of one or more reference cells, in order to determine the state(s) of the NVM's cells, are known. The most common technique includes applying the same terminal voltages and supply currents to the NVM being read and to a defined reference structure (e.g. reference cell which Vt is known) and determining which starts conduct first. FIG. 3 shows a functional block diagram of an NVM device including: (1) an array of NVM cell; (2) a set of reference structures, which structures could be from within the array; (3) one or more voltage sources for applying voltages and providing current to both the NVM cells and array structures; and (4) cell evaluation circuits(s) such as sense amps. FIG. 4 shows a composite circuit and current flow diagram depicting how applied voltages and currents may induce current flow through individually selected NVM cells within an NVM array during a reading/sensing phase.
Since the distance and number of branches through which current from an array driver may need to flow is highly variable depending upon the location and number of selected NVM cells on the array for a given operation, the resistance and capacitance experienced by the array driver likewise greatly varies from operation to operation. FIG. 5 illustrates a conventional drain driver topology along with a corresponding voltage graph indicating how the voltages transition at different points along the bit-line path during a sensing operation. The graphs also illustrate a delay and a sensing voltage error in the sensing operation introduced do to capacitance and/or resistance of the bit-lines.